Static And Dynamic Cmos Cascode Voltage Switch Logic Circuits Computer Science Essay

unruffled And Dynamic Cmos Cascode Voltage Switch Logic Circuits Computer cognition EssayThis paper presents a triple rail system of logical system network establish unmoving and propellant CMOS cascode voltage deal logic (CVSL) rophys for improving the functional efficiency and emit military unit consumption. The logic digit strategic is achieved in CVSL by cascading differential pairs of FET devices argon capable of processing Boolean functions up to (2N-1) excitant variables within a superstar perimeter delay. Potentially CVSL is twice as dense as primitive NAND/NOR logic, and is compatible with existing conception automation tools and relieving the device/process complexity burden for CVSL designs. strong performance and density improvements with simultaneous reduction in power consumption have been investi approachd using cadence-90 nm technology. The power requirements for the static and energetic cascode voltage switch logic ropes atomic number 18 comparedIn dex Terms- cascode voltage switch logic (CVSL), Dual rail logic, CMOS VLSI roundabout, cadence toolsINTRODUCTIONIn recent years, most of the digital systems are static full complementary metal-oxide-semiconductor (CMOS) due to their robust design nature which can implement reliable circuits with refined up commit margin. However, the demand for superior digital systems requires continuously faster CMOS circuit speed. Dynamic circuits are be to have better circuit performance. But unfortunately, these dynamic design styles suffer from presence sharing, low noise margin, complexity of design, and difficulty in testing. Recently, several researchers have attempted to use pass-gate logic style to check static and high performance designs in different digital systems 1-2. Pass-gate logics gain their speed over the handed-down static CMOS design due to their high logic functionality and reduction in the number of pFET transistors. However, the degradation of remove performance fo r the pass-gate design in the long circuit chain is the major obstacle for most designers to use. Recently, CMOS circuit design technique based cascode voltage switch logic (CVSL) is proposed with numerous advantages over the conventional static CMOS 3. The domino CMOS, NORA and pseudo-NMOS technique is only telling in non-complementary logic circuits and it cannot apply directly to complementary logic functions. But, CVSL circuits can be applied to complementary logic families. Potential advantages include reduced circuit delay, high layout density, lower power consumption and extended logic flexibility 4.CVSL have been used to implement high-performance arithmetic circuits such as fast multiplications, ROM, RAM as well as pipelined DSP circuits. CVSL is very capable for asynchronous designs when logic works at that time only the clocks are running remain time is off. This reduces power consumption, especially for large and complex circuits 5. Dual rail logic network families a re becoming increasingly important for advanced technologies because of the very small amount of charge infallible to afford a logic state. The cascode-voltage-switch logic gates are evaluated for improved the functional efficiency using 90 nm and 65 nm technology CMOS processes 6.This paper describes treble rail logic network based static and dynamic CMOS cascode voltage switch logic (CVSL) circuits for improving the functional efficiency and power reduction. substantial performance and density improvements with simultaneous reduction in power consumption have been investigated using cadence. The power requirements for the static and dynamic are CVSL compared.design of CMOS CVSL circuitCascode voltage switch logic is a multiple-rail logic family. The double-rail logic based differential CVSL gates are provides the potential of having high fan-in which leads to a reduction in logic depth, high speed, and the capability of generating completion signals for asynchronous operation s.A) Dual rail Logic conceptThe dual rail logic structure is consists of two-pFET are cross-coupled to form a simple fix that provides complementary outputs and the latch is driven by an nFET network that can be viewed as two complementary electric switch functions. The dual rail logic circuits are more complex than single rail logic circuit, but the dual rail circuit can be faster than single rail circuit 6.VDD0 to1 leave out0(a) slip waveform for single rail logicVDD0 to1 swing0(a) Switching waveform for dual rail logicFig 1 Switching action for single and dual rail networkThe slew rate is simply the rate of change of the output voltage in time. A large slew rate implies a fast transposition speed. In case of single rail circuit is generated output, but dual rail logic circuit, both and are generate as output of the gates that is shown in Fig 1. The logic variable is taken to be the difference signalthat effective of slew rate is defines asThis illustrate that dual rail circu it intrinsically exhibits faster switching speed than single rail network. In practical the dual rail logic has some problems change magnitude circuit complexity, increased interconnects required in the layout and timing issues become critical. These problems have been investigated in this static and dynamic differential cascode voltage switch logic circuits.B) Static CVSLStatic differential cascode switch logic circuits normally consist of a push-pull load by pFET and a pair of interrelated (requiring both true and complement signals) binary decision trees by nFET. The Differential CVSL tree is properly designed into two ways, such that(1) When the enter vector is the true of the switching function, that node is disconnected from grime and node is connected to ground by a unique conducting path through the tree.(2) When the input vector is false of, the reverse holds.The logic trees may be further minimized from the full differential form using logic minimization algorithms. Th is version, which aptitude be termed a static CVSL gate, is lower than a conventional complementary gate employing a p-tree and n-tree. This because switching action, the p pull-ups have to fight the n pull-down trees.VDDpFET LatchpFET2pFET1nFET Logic ArrayFig 3 Static CMOS CVSL gate circuitA design procedure for differential CVSL circuits using the pictorial nature of the Karnaugh use is proposed. A CMOS cell designed with this procedure is compared with the corresponding gate logic design. A CVSL circuit of the Boolean function is given by that is shown in Fig 2. Note that only 12 transistors are required for this differential CVSL circuit design, two p-transistors and ten n-transistors instead of 10 p-transistors and 10 n-transistors using a NAND-NAND grade or conventional gate logic design. The transistor pFET latching circuit is consists of two electrostatic states. The conductions of the source-gate voltage on the devices are given asThe behavior of the latches is that and is andare voltage complements in this circuit, so one is high season other is low. The latching is induced by nFET switching network, which biases pFET1 into conduction from that timeWith pFET1 conducting, rises to, which drives pFET2 into cutoff from that timeThis represents one stable state of the latch. The voltage is pulled to, which gives and biases pFET2 into conduction and pFET1 into cutoff. From this principle, there is no direct path for current flow from to ground for either situation, so that only leakage currents exist.C) Dynamic CVSLThe static CVSL logic gate can be transformed into dynamic circuit by rewiring the pFET latch to the clock-driven arrangement, shown in Fig 3. This eliminates the feedback loop and changes the two-pFET into precharge devices that are controlled by the clock. When the value of clock is zero, drives both pFET into conduction mode that import is precharging of the output nodes. To avoid DC-current flow during this event, an rating nFET is c ontrolled by the clock, so it is OFF during the precharge time.VDDnFETCombinational networkDifferentialInputsClockClock (precharge)pFET1pFET2Fig 3 Basic structure of a dynamic CVSL gate circuitThe precharge clock is zero at event, which allows the voltages crossways both and to precharge to value ofWhen the clock change to the value is one, the circuit is driven into the evaluation phase. nFET is ON and the input signals are valid. For the case true signals switch is open and is held high while complementary switch is disagreeable and discharges toThe output voltages are initially complementary. However, the left output voltage is subject to the usual dynamic problems of charge sharing and charge leakage, which reduces its value in time. As with all dynamic logic circuits, this gives rise to a minimum clock frequency. The pFET charge is controlled by the output states and. This dynamic cascade switch logic circuit allows with small aspect ratio for charge compensation without exce ssive current flowing onto the node.Simulation result and analysisThe performance of the static and dynamic cascode voltage switch logic circuits designed and evaluated through cadence-gpdk90 nm technology.The static CMOS cell designed CVSL circuit of the Boolean function is given by. The differential input signals A, B, C, D, and E and also complementary input signals are applied to the pull-down (nFET network) network of the circuit. The fugitive response voltage is set as 1 V with 0.1 ns rise/fall time. The cross-coupled latch is provides complementary outputs and that is shown in Fig 4ABCDEQFig 4 Simulation waveforms for static CVSL circuitClockABCDQFig 5 Simulation waveforms for dynamic CVSL circuitThe dynamic CMOS cell designed CVSL circuit of the Boolean function is given byas a four XOR gate implementation. This is just two-domino gates operating on true and complement inputs with a minimized logic tree. The transient response voltage is set as 1 V with 0.1 ns rise/fall tim e. The cross-coupled latch is provides complementary outputs and that is shown in Fig 5The static and dynamic CVSL circuits power consumption is calculated and given in table 1Table 1 Static and dynamic CVSL tycoon consumptionCMOS LogicPower consumptionStatic CVSL166 uWDynamic CVSL224 uWConclusionsThis paper implements a dual rail logic circuit design technique for CMOS differential cascade voltage switch circuits. This CVSL gates facilitates that improving the functional efficiency and low power consumption. The static and dynamic CMOS differential CVSL circuits have been investigated using cadence-gpdk90 nm technology.